A conventional hetero-junction bipolar transistor using a Group III-V compound semiconductor is described, for example, in National Technical Report Vol. 39 No.6 (Dec. 1993), pp. 729-735 (the first prior art). Its sectional structure is illustrated in FIG. 2(a). On a GaAs substrate 1 are formed a heavily doped n-type GaAs sub-collector layer 2, an n-type GaAs collector layer 3, a heavily doped p-type GaAs base layer 4, an n-type AlGaAs emitter layer 5, a heavily doped n-type InGaAs cap layer 6 for forming an ohmic contact, and a heavily doped n-type InGaAs layer 7. An emitter electrode 8, a base electrode 10 and a collector electrode 16 are formed on the exposed emitter layer, base layer and sub-collector layer, respectively. The reference numeral 38 denotes an area which has been rendered high in resistance by proton implantation. According to the structure of this device, the area of the emitter electrode is larger than that of an emitter electrode contact hole formed by an SiN layer 39 which is used for connection with a wiring metal 20.
Another example of a hetero-junction bipolar transistor using a Group III-V compound semiconductor is described in IEEE Electron Device Letters EDL-8 (1987), pp. 246-248 (the second prior art). Its sectional structure is illustrated in FIG. 2(b). On a GaAs substrate 1 are formed a heavily doped n-type GaAs sub-collector layer 2, an n-type GaAs collector layer 3, a heavily doped p-type GaAs base layer 4, an undoped GaAs base spacer layer 4', an n-type AlGaAs emitter layer 5, and a heavily doped n-type GaAs cap layer 6 for forming an ohmic contact. An emitter electrode 8, a base electrode 10 and a collector electrode 16 are formed on the exposed emitter layer, base layer and sub-collector layer, respectively. The reference numeral 9 denotes SiO.sub.2 side walls, numeral 38 denotes an area which has been rendered high in resistance by proton implantation, and numeral 40 denotes an SiO.sub.2 film. In this device, the outer periphery of mesa portion of the base layer 4 and collector layer 3 is of the same structure as the outer periphery of the base electrode 10.
Further, a conventional hetero-insulated gate field effect transistor is described, for example, in Japanese Patent Laid Open No. 283433/93 (the third prior art). The hetero-insulated gate field effect transistor indicates a gate field effect transistor of a structure in which a layer of a larger energy band gap than a channel layer is sandwiched in between the channel layer and a Schottky gate electrode. Its sectional structure is illustrated in FIG. 9. In the same figure, the numeral 26 denotes a single crystal semiconductor substrate, numeral 31 denotes a heavily doped n-type GaAs layer, numeral 28 denotes a channel layer comprising n-type GaAs layer, undoped AlGaAs layer and undoped GaAs layer, and numeral 24 denotes an insulating layer between SiO.sub.2 layers. In this device, a low-resistance metal 37 is laminated onto a gate electrode 29 formed of WSi to reduce the gate resistance.